1. Field of the Invention
The present invention relates to an offset chip-stacked package structure, and more particularly, to an offset chip-stacked structure with leadframe having bus bar.
2. Description of the Prior Art
In semiconductor post-processing, many efforts have been made for increasing scale of the integrated circuits such as memories while minimizing the occupied area. Accordingly, the development of three-dimensional (3D) packaging technology is in progress and the idea of making up a chip-stacked structure has been disclosed.
The prior art has taught that a chip-stacked structure can be formed by firstly stacking a plurality of chips and then electrically connecting the chips to the substrate in a wire-bonding process. FIG. 1A is a cross-sectional view of a prior chip-stacked package structure stacked by chips of same or similar size. As shown in FIG. 1A, a conventional chip-stacked package structure 100 includes a package substrate 110, chips 120a and 120b, a spacer 130, wires 140, and an encapsulant 150. The package substrate 110 has a plurality of pads 112 thereon, and the chips 120a and 120b are also respectively provided with the pads 122a and 122b arranged in peripheral type. The chip 120a is provided on the substrate 110, while the chip 120b is provided on the chip 120a with a spacer 130 intervened there-between. The chip 120a is electrically connected to the substrate 110 by bonding two ends of one of the wires 140 to the pads 112 and 122a respectively. The chip 120b is electrically connected to the substrate 110 in similar manner. The encapsulant 150 is then provided on the substrate 110 to cover the chips 120a and 120b and the wires 140.
Since the pads 122a and 122b are respectively provided at the peripheral of the chip 120a and the 120b, there is a need to apply the spacer 130 to prevent the chip 120b from directly contacting with the chip 120a for performing the subsequent wire-bonding. However, the use of spacer 130 increases the thickness of the chip-stacked package structure 100.
Another prior chip-stacked package structure for different-sized chips has been disclosed. Referring to FIG. 1B, another conventional chip-stacked package structure 10 includes a package substrate 110, chips 120c and 120d, wires 140, and an encapsulant 150. The substrate 110 has pads 112 on it. The chip 120c is larger than the chip 120d in size. The chips 120c and 120d are respectively provided with peripherally arranged pads 122c and 122d. The chip 120c is provided on the substrate 110 while the chip 120d is provided on the chip 120c. The chip 120c is electrically connected to the substrate 110 by bonding two ends of one of the wires 140 to the pads 112 and 122c respectively. The chip 120d is electrically connected to the substrate 110 in similar manner. The encapsulant 150 is then provided on the substrate 110 to cover the chips 120c and 120d and the wires 140.
Since the chip 120d is smaller than the chip 120c, the chip 120d would not covered over the pads 122c of the chip 120c when the chip 120d is stacked on the chip 120c. However, the condition that the upper chip must have size smaller than that of the lower chip limits number of the chips to be stacked in the chip-stacked package structure 10.
In other words, the above-mentioned chip-stacked package structures have drawbacks of either increasing thickness as shown in FIG. 1A or limiting number of the chips to be stacked as shown in FIG. 1B.